1. Technical Field
The present invention relates generally to the field of computer manufacturing and more specifically to reducing the coefficient of thermal expansion of boards used in computers.
2. Background Art
Computers and similar electronic equipment have become ubiquitous elements in the lives of people. Many businesses, banks, and governments rely on computers for their everyday activities. A large portion of the global community require that computers be reliable, stable facets of their economic, societal, and communication foundations. Computers today are required to run longer, with less down-time, than at any time in the past.
Because computers are so necessary, there has been an increased emphasis by computer designers on reliability. Many systems today cannot tolerate the extended down time necessary to replace failed components that make up the computer system. If each component is designed to last longer and be more reliable, then each computer, which is made exclusively of components, will last longer and be more reliable.
This emphasis on reliability of components has been applied to Printed Circuit Boards (PCBs). Most components in a computer system are designed by placing semiconductor packages, containing a semiconductor chip, onto a PCB or by placing chips directly onto Laminated Chip Carriers (LCCs) and connecting the LCCs to the PCB. PCBs are called "printed" because circuit runs or lines of copper are placed on the boards using techniques that were originally similar to the newsprint process. These circuit lines connect the semiconductor packages or chips together. PCBs can be as simple as an insulator that has lines printed on one or both sides and one or more packages attached to one or both sides. PCBs are generally more complex, however, and are usually made of conductive, metal power and ground planes and several signal planes containing circuit lines sandwiched between several layers of insulator, with metal lines and pads on the top and bottom surface of the sandwich. Top and bottom conductors are connected with each other and internal circuit layers with metal plated through holes (PTHs).
PCBs made in this manner have become the standard in electronics. Advances in manufacturing methods have made PCBs relatively inexpensive yet their simplicity makes them reliable. There are, however, problems associated with PCBs. One of the causes of some of these problems is the coefficient of thermal expansion (CTE) for the overall PCB and the individual layers.
Many PCBs and especially LCCs, which are generally composed of organics, need to have a lower CTE that is better matched to the CTE of the silicon chip. When trying to reduce the CTE of the PCB, a variety of dielectrics with lower CTEs are available. However, the effectiveness of using these lower CTE dielectrics is limited because the power and ground planes, which constitute a significant portion of the PCB, are still composed of copper. Copper has a relatively high CTE compared with some of the lower CTE dielectric materials. The relatively high CTE of copper, the high amount of copper, and the high tensile modulus of copper act to maintain a high composite CTE for the board or LCC.
The high CTE power and ground planes cause the overall CTE of the PCB to be similar to the CTE of these metal planes. Because the overall CTE is fairly high, the PCB or LCC itself tends to lengthen and grow in size with increasing temperature. This increase in size means that the chips, packages, lines, and other devices on the surfaces of the PCB or LCC need to expand at the same rate or be able to tolerate the stress caused by the mismatch in size. Sometimes these devices or the electrical connections between them cannot withstand the stress, particularly after repeated temperature cycling.
These stresses are particularly deleterious for LCCs. The chip is connected to the LCC through small solder bumps called Controlled Collapse Chip Connections (C4). The LCC is then connected to a PCB, generally through ball grid arrays (BGAs). An encapsulation and/or undercoating is placed under and around the chip to protect the chip.
Chip carriers were previously made almost exclusively of ceramics, which have low CTEs. Low CTE chip carriers do not place as much stress on the chips because the ceramic layers do not expand that much. Currently, however, laminate materials are being used as chip carriers. Laminate materials have higher CTEs, as explained above, and put more stress on chips connected to the LCC. Unfortunately, because chips are primarily made of crystalline silicon, which is easily fractured, this stress can either fracture the C4 connections or the chip/LCC CTE mismatch will cause the assembled package to warp putting tensile stress on the chip, possibly cracking the chip.
In addition, the metal layers commonly used in PCB manufacturing have much higher CTEs than some of the low CTE dielectrics. Because of the differences in CTEs, a temperature increase will cause the metal to lengthen at a faster rate than the dielectrics. This difference in expansion can put high stresses on the dielectrics, which can lead to cracking of the dielectric materials. Cracking of dielectrics can cause opens because lines can be pulled apart. Another effect caused by the CTE differential is shear induced debonding, where the dielectric is torn from the power/ground planes. Shear induced debonding exacerbates the CTE-caused cracking mechanisms because the debonded dielectric is essentially "floating" and is not connected to the metallic power/ground planes. The periphery of the debonded area is, however, connected to a metallic plane and tends to move with metallic plane as the metallic pane lengthens with increasing temperature. Cracking then can develop around the periphery as the periphery moves away from the debonded dielectric.
While low CTE metals such as invar, stainless steel, and molybdenum have been used to construct lower CTE power planes for PCBs and LCCs, use of these alternative metals can create a variety of manufacturing complications. These complications include galvanic activity and corrosion, multi-step etching, and complicated waste treatment.
Therefore, without a way to limit failures and fractures caused by CTE differences between dielectrics and power/ground layers and the overall relatively high CTE in PCBs and LCCs, PCBs and LCCs will continue to have a higher numbers of failures and reliability problems.